1. Field of the Invention
The present invention relates to a delay circuit, and particularly relates to a delay circuit for use in a semiconductor integrated circuit.
2. Description of the Related Art
In a semiconductor integrated circuit (including a semiconductor memory), a delay circuit which delays a signal by a desired time is used for regulating the timing of propagation of the signal. A delay circuit is generally configured by an inverter, a resistance element, a capacitor element and the like. As a result of enhancement in the operation speed in semiconductor integrated circuits of recent years, extremely high precision is required in regulation of delay times. Therefore, delay circuits need to be manufactured with higher precision so as to obtain more accurate delay times. Further, by microfabrication of a semiconductor integrated circuit, reduction in the circuit area of a delay circuit, and suppression of influence on metal restriction are demanded.
As a related art, Japanese Patent Laid-Open No. 2002-94002 discloses a semiconductor device. The semiconductor device includes a signal line, and a capacitor element and a resistance element which are connected to the signal line. This semiconductor device is characterized in that a part or whole of the resistance element configures a part of the capacitor element. The capacitor element and the resistance element function as a delay circuit. The capacitor element may be an MIS capacitance. The resistance element may be formed from a wiring layer used as a gate of an MIS transistor. The resistance element may be formed from a polysilicon layer. The capacitance value of the capacitor element and the resistance value of the resistance element may be physically or electrically variable. Japanese Patent Laid-Open No. 2002-94002 describes that by the semiconductor device, the layout area of the delay circuit can be reduced.
However, it has been found out by the study of the inventor that the technique of Japanese Patent Laid-Open No. 2002-94002 has the following problem. FIG. 1 is a schematic sectional view schematically showing the configuration of the semiconductor device of Japanese patent Laid-Open No. 2002-94002. In this art, a diffusion layer 112 is provided in a well 111 on a semiconductor substrate 110, and a gate wiring layer (polysilicon layer) 113 is provided on the diffusion layer 112 via a gate insulating film 115. More specifically, a capacitor element (C) configured by the gate wiring layer 113, the gate insulating film 115 and the diffusion layer 112, and a resistance element (R) configured by the gate wiring layer 113 continuously configure the delay circuit 101. FIG. 2 is a circuit diagram showing the equivalent circuit of FIG. 1. In the delay circuit 101, C1 can charge and discharge electricity from and to R1, and Cn can charge and discharge electricity from and to Rn (n is a natural number). However, Co charges and discharges to and from an impedance component in an inverter INV1. More specifically, a transistor in the inverter INV1 relates to charge and discharge. However, in a transistor, variation easily occurs to the impedance component due to the influence of voltage, temperature, a production error and the like as compared with a normal capacitor element and resistance element of simple structures. Therefore, the delay circuit 101 has difficulty in making the delay time more accurate, and is considered to have a problem of precision.
Further, in order to enhance precision, the resistance element is preferably in a straight-line shape of which size precision can be easily realized. However, the resistance element (gate wiring layer) of Japanese Patent Laid-Open No. 2002-94002 is in a meandering shape. Accordingly, it is considered to be difficult to realize high size precision. Further, in recent years, for the gate wiring layer, the stacked layers of a polysilicon layer and a silicide layer are used instead of only one polysilicon layer. Therefore, it is conceivable that application of such a gate wiring layer to the resistance element of Japanese Patent Laid-Open No. 2002-94002 makes the resistance value too low. Further, if metal wiring coupling noise is on a delay contact point, an error occurs. Therefore, when the metal wiring is used in the delay circuit, there arises the problem of metal wiring restriction which restricts use of the metal wiring in its upper layer. Further, when a metal wiring is used in the delay circuit, there is the problem of the occurring noise easily propagating to the metal wiring.
A delay circuit which provides more accurate delay times is desired. A delay circuit is required, in which the circuit area is reduced, and influence on the metal restriction is suppressed is required. A delay circuit in which noise hardly propagates is desired.